Optimistic Channel Usage between Simulator and Simulation Accelerator

This paper presents an optimized channel usage scheme between simulator and simulation accelerator, assuming that the target system is composed of building blocks interconnected by a system bus. Unlike the conventional scheme, where the progresses of simulator and accelerator are synchronized at every simulation time, the proposed method synchronizes them only at boundaries of burst transfers on the system bus. For the most part, the progresses of simulator and accelerator are not synchronized and the one leading the other predicts the status of the other, which verifies the prediction afterwards. Prediction error leads to rollback which restores the state of the simulator or accelerator to a previous one. The abstraction level of prediction and verification is as low as pin level to guarantee 100% cycle accuracy. The proposed method brings substantial performance gain by minimizing the number of channel accesses, which has a large startup overhead.